Gate driver circuit, level shifter, and display apparatus

ABSTRACT

Disclosed are a gate driver circuit, a level shifter and a display apparatus. The gate driver circuit includes a potential enhancing unit, a switch unit, a current detecting unit, and a control unit. The potential enhancing unit is configured to divide a clock signal output by a timing sequence controller into two clock signal groups after the clock signal being potential enhanced, and correspondingly output the two clock signal groups to two shift register groups; the switch unit is configured to control to output or stop outputting the clock signal groups; the current detecting unit is configured to respectively detect output current of each sub-clock signal; the control unit is configured to compare current values corresponding to the plurality of current signals with a preset current threshold respectively, output a control signal to the switch unit.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation Application of PCT ApplicationNo. PCT/CN2018/115121 filed on Nov. 13, 2018, which claims the benefitof Chinese Patent Application No. 201811072275.0, filed on Sep. 13,2018, which is incorporated herein by reference in its entirety.

FIELD

The present disclosure relates to the field of display panel technology,and more particularly relates to a gate driver circuit, a level shifter,and a display apparatus.

BACKGROUND

With the increasing demand for narrow-border televisions, a new type ofgate driver on array driver (GOA) architecture is getting more and morepopular. In the general display panel, a gate IC is bound on a panel,thus, a further narrowing of the border would be limited by the size ofthe gate IC. In recent years, with the advent of the new type of GOAtechnology, the traditional driving way has been gradually replaced. TheGOA circuit is a circuit in which the original Gate IC is divided intotwo parts including a level shifter chip (level shifter IC) and a shiftregister. The level shifter chip is manufactured on the driver board,and the shift register is on the panel. The level shifter chip transmitsCLK to the shift register for driving. As such, the structure of theGate IC is simplified, and further, the border length is reduced.

In the manufacture process of the GOA, shift registers are provided onboth the left and right sides of the panel, so as to implement bilateraldriving. Considering that instability may occur in the manufactureprocess, and damage may be caused to one shift register duringoperation, an abnormal display may be generated. Because there is aprobability for the shift register on either side to be damaged, it isimpossible to fix one of the driving ways. Currently, three driverboards are developed in one panel, which are respectively used to drivethe shift register on left side only, the shift register on the rightside only, and the shift registers on both the left and right sides. Itis passively determined that which driver board works according toactual damage status of the shift register, which is costly, laboriousand time-consuming.

SUMMARY

It is one main objective of the present disclosure to provide a gatedriver circuit, aiming to improve compatibility of the driver board, andreduce design costs.

In order to realize the above aim, the present disclosure provides agate driver circuit, the gate driver circuit includes:

a potential enhancing unit, configured to divide a clock signal outputby a timing sequence controller into two clock signal groups after theclock signal being potential enhanced by the potential enhancing unit,and correspondingly output the two clock signal groups to two shiftregister groups on a display panel, to drive the display panel to work;the two clock signal groups respectively comprising at least onesub-clock signal;

a switch unit, connected in series between the potential enhancing unitand the shift registers located at both ends of the display panel, andconfigured to correspondingly switch on or off according to a controlsignal received, to control to output or stop outputting the clocksignal groups;

a current detecting unit, connected in series between the potentialenhancing unit and the switch unit, or in series between the switch unitand the shift registers located at both ends of the display panel,configured to respectively detect output current of each sub-clocksignal in the two clock signal groups, and feed back a plurality ofcurrent signals to the control unit; and

a control unit, configured to receive the plurality of current signalsoutput by the current detecting unit, and compare current valuescorresponding to the plurality of current signals with a preset currentthreshold respectively, when the current value of any one of thesub-clock signals in one of the clock signal groups is less than thepreset current threshold, output a control signal to the switch unit, tocontrol the switch unit to cut off the output of the clock signal group.

Optionally, a signal input end of the potential enhancing unit connectsto a signal output end of the timing sequence controller, a signaloutput end of the potential enhancing unit connects to a signal inputend of the current detecting unit, a signal output end of the currentdetecting unit connects to a signal input end of the switch unit, afirst signal output end of the switch unit connects to a signal inputend of the first shift register group of the display panel, a secondsignal output end of the switch unit connects to a signal input end ofthe second shift register group of the display panel, a controlled endof the potential enhancing unit, the signal output end of the currentdetecting unit, and a controlled end of the switch unit all connect to asignal end of the control unit.

Optionally, the switch unit comprises a first sub-switch unit and asecond sub-switch unit, the potential enhancing unit output twoidentical clock signal groups to the shift register located at both endsof the display panel, respectively via the first sub-switch unit and thesecond sub-switch unit, the controlled end of the first sub-switch unitand the controlled end of the second sub-switch unit both connect to acontrol end of the control unit.

Optionally, the switch unit comprises a plurality of sub-switch units,each of sub-clock signals is output to the shift registers via each ofthe sub-switch units, and the controlled end of each of the sub-switchunits respectively connects to a control end of the control unit.

Optionally, the plurality of sub-switch units defined between thecurrent detecting unit and the first shift register are linked, and theplurality of sub-switch units defined between the current detecting unitand the second shift register are linked.

Optionally, each of the sub-switch units is a metal-oxide semiconductorfield effect transistor.

Optionally, each of the sub-switch units is a triode.

Optionally, the current detecting unit comprises a plurality ofsub-current detecting units, each of the sub-current detecting unitsrespectively detects current of each of the sub-clock signals, andrespectively feeds back current signal to the control unit.

The present disclosure further provides a level shifter, which includesthe gate driver circuit as described above. The gate driver circuitincludes:

a potential enhancing unit, configured to divide a clock signal outputby a timing sequence controller into two clock signal groups after theclock signal being potential enhanced by the potential enhancing unit,and correspondingly output the two clock signal groups to two shiftregister groups on a display panel, to drive the display panel to work;the two clock signal groups respectively comprising at least onesub-clock signal;

a switch unit, connected in series between the potential enhancing unitand the shift registers located at both ends of the display panel, andconfigured to correspondingly switch on or off according to a controlsignal received, to control to output or stop outputting the clocksignal groups;

a current detecting unit, connected in series between the potentialenhancing unit and the switch unit, or in series between the switch unitand the shift registers located at both ends of the display panel,configured to respectively detect output current of each sub-clocksignal in the two clock signal groups, and feed back a plurality ofcurrent signals to the control unit; and

a control unit, configured to receive the plurality of current signalsoutput by the current detecting unit, and compare current valuescorresponding to the plurality of current signals with a preset currentthreshold respectively, when the current value of any one of thesub-clock signals in one of the clock signal groups is less than thepreset current threshold, output a control signal to the switch unit, tocontrol the switch unit to cut off the output of the clock signal group.

Optionally, a signal input end of the potential enhancing unit connectsto a signal output end of the timing sequence controller, a signaloutput end of the potential enhancing unit connects to a signal inputend of the current detecting unit, a signal output end of the currentdetecting unit connects to a signal input end of the switch unit, afirst signal output end of the switch unit connects to a signal inputend of the first shift register group of the display panel, a secondsignal output end of the switch unit connects to a signal input end ofthe second shift register group of the display panel, a controlled endof the potential enhancing unit, the signal output end of the currentdetecting unit, and a controlled end of the switch unit all connect to asignal end of the control unit.

Optionally, the switch unit comprises a first sub-switch unit and asecond sub-switch unit, the potential enhancing unit output twoidentical clock signal groups to the shift register located at both endsof the display panel, respectively via the first sub-switch unit and thesecond sub-switch unit, the controlled end of the first sub-switch unitand the controlled end of the second sub-switch unit both connect to acontrol end of the control unit.

Optionally, the switch unit comprises a plurality of sub-switch units,each of sub-clock signals is output to the shift registers via each ofthe sub-switch units, and the controlled end of each of the sub-switchunits respectively connects to a control end of the control unit.

Optionally, the plurality of sub-switch units defined between thecurrent detecting unit and the first shift register are linked, and theplurality of sub-switch units defined between the current detecting unitand the second shift register are linked.

Optionally, each of the sub-switch units is a metal-oxide semiconductorfield effect transistor.

Optionally, each of the sub-switch units is a triode.

Optionally, the current detecting unit comprises a plurality ofsub-current detecting units, each of the sub-current detecting unitsrespectively detects current of each of the sub-clock signals, andrespectively feeds back current signal to the control unit.

Optionally, the potential enhancing unit, the current detecting unit,the switch unit, and the control unit are integrated in the levelshifter.

The present disclosure further provides a display apparatus, whichincludes the level shifter as described above. The level shifterincludes a gate driver circuit, the gate driver circuit includes:

a potential enhancing unit, configured to divide a clock signal outputby a timing sequence controller into two clock signal groups after theclock signal being potential enhanced by the potential enhancing unit,and correspondingly output the two clock signal groups to two shiftregister groups on a display panel, to drive the display panel to work;the two clock signal groups respectively comprising at least onesub-clock signal;

a switch unit, connected in series between the potential enhancing unitand the shift registers located at both ends of the display panel, andconfigured to correspondingly switch on or off according to a controlsignal received, to control to output or stop outputting the clocksignal groups;

a current detecting unit, connected in series between the potentialenhancing unit and the switch unit, or in series between the switch unitand the shift registers located at both ends of the display panel,configured to respectively detect output current of each sub-clocksignal in the two clock signal groups, and feed back a plurality ofcurrent signals to the control unit; and

a control unit, configured to receive the plurality of current signalsoutput by the current detecting unit, and compare current valuescorresponding to the plurality of current signals with a preset currentthreshold respectively, when the current value of any one of thesub-clock signals in one of the clock signal groups is less than thepreset current threshold, output a control signal to the switch unit, tocontrol the switch unit to cut off the output of the clock signal group.

In the technical solution of the present disclosure, the gate drivercircuit is formed by the potential enhancing unit, the current detectingunit, the switch unit and the control unit.

Potential of a low level logic signal from a timing sequence controlleris enhanced by the potential enhancing unit, and then divided into twoclock signal groups in which each of the two clock signal groupsincludes at least one sub-clock signal. The two clock signal groups areoutput to two shift register on the display panel, so as to drive thedisplay panel. Current value of each of the clock signals is detected bythe current detecting unit, and then fed back to the control unit. Whenone of the shift registers on the display panel is damaged, the currentof the clock signal output to the shift register is abnormal. Thecontrol unit correspondingly outputs a control signal to the switchunit, according to the current signal fed back by the current detectingunit, so as to switch off the clock signal output to the shift register,realizing unilateral driving. As such, different abnormal states of theshift registers located at both ends of the display panel could bedynamically matched, improving the compatibility of the driver board.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the presentdisclosure or the technical solutions in the prior art, the drawingsused in the embodiments or the prior art description will be brieflyintroduced below. Obviously, the drawings in the following descriptionare merely some of the embodiments of the present disclosure, and thoseskilled in the art can obtain other drawings according to the structuresshown in the drawings without any creative work.

FIG. 1 is a functional module diagram of a gate driver circuit of anembodiment according to the present disclosure;

FIG. 2 is a functional module diagram of a gate driver circuit ofanother embodiment according to the present disclosure;

FIG. 3 is a functional module diagram of a gate driver circuit ofanother embodiment according to the present disclosure;

FIG. 4 is a functional module diagram of a level shifter of anembodiment according to the present disclosure.

The realizing of the aim, functional characteristics and advantages ofthe present disclosure are further described in detail with reference tothe accompanying drawings and the embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The technical solutions in the embodiments of the present disclosurewill be described clearly and completely combining the drawings in theembodiments of the present disclosure. Obviously, the describedembodiments are only a part of the embodiments of the presentdisclosure, but not all of them. Based on the embodiments in the presentdisclosure, all other embodiments obtained by those skilled in the artwithout creative work shall belong to the protection scope of thepresent disclosure.

It should be noted that, terms such as “first” and “second” are usedherein for purposes of description and are not intended to indicate orimply relative importance or to imply the number of indicated technicalfeatures. Thus, the features defined with “first” and “second” maycomprise or imply at least one of these features. Moreover, the meaningof “and/or” appearing in the full text is: including three parallelsolutions. Taking “A/B” as an example, it includes the A plan, or the Bplan, or the plan satisfying A and B simultaneously. In addition, thetechnical solutions between the various embodiments of the presentdisclosure may be combined with each other, but must be based on therealization of those skilled in the art. When the combination oftechnical solutions is contradictory or impossible to implement, itshould be considered that the combination of the technical solutionsdoes not exist, and not within the scope of protection required by thisdisclosure.

The gate driver circuit 100 of the present disclosure is configured todrive a small-size display panel. For a small-size display panel, theload of the gate line is small, therefore, a bilateral driving or aunilateral driving could be adopted. As shown in FIG. 1, FIG. 1 is afunctional module diagram of a gate driver circuit of an embodimentaccording to the present disclosure, the gate driver circuit 100includes:

a potential enhancing unit 110, configured to divide a clock signaloutput by a timing sequence controller 200 into two clock signal groupsafter the clock signal being potential enhanced by the potentialenhancing unit 100, and correspondingly output the two clock signalgroups to two shift register groups on a display panel, to drive thedisplay panel to work; the two clock signal groups respectivelycomprising at least one sub-clock signal;

a switch unit 140, connected in series between the potential enhancingunit 110 and the shift registers located at both ends of the displaypanel, and configured to correspondingly switch on or off according to acontrol signal received, to control to output or stop outputting theclock signal groups;

a current detecting unit 130, connected in series between the potentialenhancing unit 110 and the switch unit 140, or in series between theswitch unit 140 and the shift registers located at both ends of thedisplay panel, configured to respectively detect output current of eachsub-clock signal in the two clock signal groups, and feed back aplurality of current signals to the control unit 120; and

a control unit 120, configured to receive the plurality of currentsignals output by the current detecting unit 130, and compare currentvalues corresponding to the plurality of current signals with a presetcurrent threshold respectively, when the current value of any one of thesub-clock signals in one of the clock signal groups is less than thepreset current threshold, output a control signal to the switch unit140, to control the switch unit 140 cut off the output of the clocksignal group.

In this embodiment, the display panel includes but not limited to aliquid display panel, an organic light emitting diode display panel, afield emission display panel, a plasma display panel, and a curvedsurface panel. The liquid display panel includes a thin film transistorliquid crystal display panel, a twisted nematic (TN) display panel, avertical alignment (VA) display panel, an in-plane switching (IPS)display panel and so on. The shift registers disposed at both ends ofthe display panel receive the plurality of clock signals output by thegate driver circuit 100, and drive pixels inside the display panel towork. The clock signals respectively received by the two shift registergroups are identical, and each clock signal is one cycle ahead of theprevious clock signal.

It is assumed that the clock signals output by the gate driver circuit100 to the two shift register groups are respectively CLK1 to CLK4, CLK2is ¼ cycle ahead of CLK1, and CLK3 is ¼ cycle ahead of CLK2. The gatedriver circuit 100 may output 6 sub-clock signals or 8 sub-clock signalsaccording to requirements. By using more CLK signals, the load of eachof signal lines and power consumption could be reduced, however, thenumber of pins in the circuit would be increased. In actual design, thenumber of clock signals output could be selected according to boarderwidth, product size, integrated circuit design, resolution of thespecific product, and so on.

The potential enhancing unit 110 receives a low level clock signaloutput by the timing sequence controller 200, and shifts the level ofthe clock signal under the modulation of the control unit 120, so as toenhance the potential of the low level clock signal and output twoidentical clock signal groups. Each clock signal group includes at leastone sub-clock signal, the number of the sub-clock signals could bedetermined according to requirements, for example, 4, 6, 8, and so on.The clock signal groups, which is output by the potential enhancing unit110, are output to the two shift register groups located at both ends ofthe display panel through the current detecting unit 130, and the switchunit 140. The current detecting unit 130 respectively detects thecurrent value of each of the sub-clock signals. The current detectingcircuit may select a circuit such as a sampling resistor or atransformer, and so on, for current detection. The switch unit 140 mayselect a plurality of switch components or switch circuits withswitching capability, such as relays, field effect transistors, triodes,and so on. In some embodiments, one switch controls the signal output ofone clock signal group, or one switch controls the output of onesub-clock signal. A controlled end of the switch is connected to acontrol end of the control unit 120, and performs switch-on orswitch-off according to the control signal output by the control unit120. The control unit 120 may select a microprocessor, a programmablesingle chip microcomputer, and so on. And a comparator circuit could bebuild on the periphery for voltage comparison, and specifically arrangedaccording to actual conditions. Thus, they are not limited herein.

In one optional embodiment, a signal input end of the potentialenhancing unit 110 is connected to a signal output end of the timingsequence controller 200, a signal output end of the potential enhancingunit 110 is connected to a signal input end of the current detectingunit, a signal output end of the current detecting unit 130 is connectedto a signal input end of the switch unit 140, a first signal output endof the switch unit 140 is connected to a signal input end of the firstshift register group 310 of the display panel, a second signal outputend of the switch unit 140 is connected to a signal input end of thesecond shift register group 320 of the display panel, a controlled endof the potential enhancing unit 110, the signal output end of thecurrent detecting unit 130, and the controlled end of the switch unit140 are all connected to a signal end of the control unit 120.

It should be noted that, the current detecting unit 130 may be disposedat the front end or the rear end of the switch unit 140, which could bespecifically determined according to the position of the driver board.Thus, it is not limited herein. In this embodiment, the currentdetecting unit 130 is disposed at the front end of the switch unit 140,the signal output end of the switch unit 140 is respectively connectedto the signal input ends of the two shift register groups. When theshift registers located at both ends of the display panel are normal,the bilateral driving is realized. When one of the shift register groupsis damaged, all or a single sub-clock signal, correspondingly output tothe shift register, could not be input normally, causing an abnormaldriving. The current detecting unit 130 detects the value of the clocksignal, and feeds back the current value of each sub-clock signal to thecontrol unit 120. The control unit 120, according to a comparisonbetween the current value with a preset current threshold, determinesthat the shift register is abnormal, and outputs the control signal tothe switch unit 140. Correspondingly, the sub-switch unit 140 inside theswitch unit 140 performs a switch-on or switch-off action, cuts off theclock signal group output to the shift register, so as to realize theunilateral driving. If the two shift register groups are both damaged,the two clock signal groups are both cut off, and the shift registersare to be repaired or replaced.

The gate driver circuit 100 may be configured to drive a small-sizedisplay panel. When the shift registers located at both ends of thedisplay panel are normal, the bilateral driving is implemented; when oneof the shift register groups has an abnormality, the unilateral drivingis automatically switched to. The gate driver circuit 100 is mounted onthe driver board, which could drive the left side, the right side, orboth the left side and the right side. As such, there is no need todesign three kinds of driver boards, improving the compatibility of thedriver board, and reducing the design costs.

In the technical solution of the present disclosure, the gate drivercircuit 100 is formed by the potential enhancing unit 110, the currentdetecting unit 130, the switch unit 140 and the control unit 120. Thepotential enhancing unit 110 enhances the potential of the clock signaloutput by the timing sequence controller 200, divides the clock signalinto two clock signal groups, and correspondingly outputs the two clocksignal groups to the two shift register groups on the display panel, tobilaterally drive the display panel. The current detecting unit 130detects current value of each clock signal, then feeds back the currentvalue to the control unit 120. When one of the shift register groups onthe display panel is damaged, the current of the clock signal output tothe shift register group is abnormal. The control unit 120correspondingly outputs the control signal to the switch unit 140according to the current signal fed back by the current detecting unit130, so as to switch off the clock signal output to the shift registergroup, realizing the unilateral driving. As such, different abnormalstates of the shift registers located at both ends of the display panelcould be dynamically matched, improving the compatibility of the driverboard.

In one optional embodiment, as shown in FIG. 2, FIG. 2 is a functionalmodule diagram of a gate driver circuit of another embodiment accordingto the present disclosure. The switch unit 140 includes a firstsub-switch unit 141 and a second sub-switch unit 142. The potentialenhancing unit 110 outputs two identical clock signal groups to theshift registers located at both ends of the display panel via the firstsub-switch unit 141 and the second sub-switch unit 142, respectively. Acontrolled end of the first sub-switch unit 141 and a controlled end ofthe second sub-switch unit 142 are both connected to a control end ofthe control unit 120.

In this embodiment, the two clock signal groups are output to thecorresponding shift register via the first sub-switch unit 141 and thesecond sub-switch unit 142, respectively. The first sub-switch unit 141and the second sub-switch unit 142 simultaneously control the output ofthe plurality of sub-clock signals. Initially, the first sub-switch unit141 and the second sub-switch unit 142 remain on status. When one of thetwo shift register groups is damaged, for example, the first shiftregister group 310, the current of the clock signal group output to thefirst shift register group 310 is abnormal. The abnormalities mayinclude that, the current of one of the sub-clock signals is small, orthe currents of multiple of the sub-clock signals are small. When thecurrent value of any one of the sub-clock signals is smaller than thepreset current threshold, the control unit 120 outputs the controlsignal to the first sub-switch unit 141, to switch off the firstsub-switch unit 141, so as to cut off at least one sub-clock signaloutput to the first shift register group 310, therefore, the unilateraldriving is implemented. Similarly, when the second shift register group320 is damaged, the second sub-switch unit 142 is switched off.

The first sub-switch unit 140 and the second sub-switch unit 142 may usemultiple-input and multi-output relays or other switch components, andcould be designed according to actual conditions, which is not limitedherein.

In one optional embodiment, as shown in FIG. 3, FIG. 3 is a functionalmodule diagram of a gate driver circuit of another embodiment accordingto the present disclosure. The switch unit 140 includes a plurality ofsub-switch units 140. Each of sub-clock signals is output to the shiftregisters via each of the sub-switch units 140, and the controlled endof each of the sub-switch units 140 respectively are connected to thecontrol end of the control unit 120.

In this embodiment, the switch unit 140 includes a plurality ofsub-switch units 140, such as K1 to K8. The sub-switch units 140corresponds to the clock signals output by the potential enhancing unit110 one by one. Each sub-switch unit 140 is connected in series betweenthe current detecting unit 130 and the shift registers, and configuredto control the output of each sub-clock signal. The plurality ofsub-switch units 140 disposed between the current detecting unit 130 andthe first shift register group 310 are linked. For example, K1 to K4 inFIG. 3 are switched on or off simultaneously; and the plurality ofsub-switch units 140 disposed between the current detecting unit 130 andthe second shift register 320 are linked. For example, K5 to K8 in FIG.3 are switched on or off simultaneously, so as to realize a synchronouscontrol of the plurality of sub-clock signals in the clock signal group,and realize an automatic switching between the bilateral driving and theunilateral driving under the control of the control unit 120.

Further, each sub-switch unit is a metal-oxide semiconductor fieldeffect transistor.

When the number of the sub-switch units included in the switch unit 140is equal to the number of the sub-clock signals, each sub-switch unitmay use a metal-oxide semiconductor field effect transistor. The gate ofthe metal-oxide semiconductor field effect transistor is taken as thecontrolled end of the sub-switch unit, and connected to the control endof the control unit 120. The source or the drain of the metal-oxidesemiconductor field effect transistor is connected to the signal outputend of the current detecting unit 130, the drain or the source of themetal-oxide semiconductor field effect transistor is connected to thefirst shift register group 310 or the second shift register group 320.The metal-oxide semiconductor field effect transistor may be a n-channelmetal-oxide semiconductor field effect transistor or a p-channelmetal-oxide semiconductor field effect transistor. When the n-channelmetal-oxide semiconductor field effect transistor is selected, thecontrol unit 120 outputs a high level to the metal-oxide semiconductorfield effect transistor to switch it on, and outputs a low level to themetal-oxide semiconductor field effect transistor to switch it off. Whenthe p-channel metal-oxide semiconductor field effect transistor isselected, the control unit 120 outputs a low level to the metal-oxidesemiconductor field effect transistor to switch it on, and outputs ahigh level to the metal-oxide semiconductor field effect transistor toswitch it off. The type of the metal-oxide semiconductor field effecttransistor could be flexibly selected, which is not limited herein.

Further, each sub-switch unit is a triode.

When the number of the sub-switch units included in the switch unit 140is equal to the number of the sub-clock signals, each sub-switch unitmay use a triode. The base of the triode is taken as the controlled endof the sub-switch unit and connected to the control end of the controlunit 120, the collector or the emitter of the triode is connected to thesignal output end of the current detecting unit 130, the emitter or thecollector of the triode is connected to the signal input end of thecorresponding shift register. The triode may be a NPN transistor or aPNP transistor. When the NPN transistor is selected, the control unit120 outputs a high level to the NPN transistor to switch it on, andoutputs a low level to switch it off. Accordingly, when the PNPtransistor is selected, the control unit 120 outputs a low level to thePNP transistor to switch it on, and outputs a high level to switch itoff. The type of triode could be flexibly selected, which is not limitedherein.

In an optional embodiment, the current detecting unit 130 includes aplurality of sub-current detecting units. Each of the sub-currentdetecting units respectively detects the current of each of thesub-clock signals, and respectively feeds back current signal to thecontrol unit 120.

It should be noted that, the plurality of sub-current detecting unitsare configured to detect the sub-clock signals output by the potentialenhancing unit 110, the number of the sub-current detecting units isequal to the number of the sub-clock signals, and the sub-currentdetecting units corresponds to the sub-clock signals one by one. Eachsub-current detecting unit detects the corresponding sub-clock signaland feeds back the current signal to the control unit 120. Thesub-current detecting unit may perform current detection by a circuit,such as a current transformer, a sampling resistor and so on.

Further, as shown in FIG. 4, FIG. 4 is a functional module diagram of alevel shifter of an embodiment according to the present disclosure. Thepresent disclosure further provides a level shifter 400, which includesthe gate driver circuit 100 as described above.

It should be noted that, GOA circuit is a circuit that divides theoriginal Gate IC into two parts of a level shifter 400 and a shiftregister. The level shifter 400 is disposed on the driver board, and theshift register is on the panel. The level shifter 400 transmits CLK tothe shift register to complete driving, so as to simplify the Gate ICstructure, further reducing the boarder length. Therefore, the potentialunit 110 in the gate driver circuit 100 could serve as a potentialshifter IC 400 independently, or, the potential enhancing unit 110, thecurrent detecting unit 130, the switch unit 140 and the control unit 120are integrated in the level shifter 400, further reducing the boarderlength. In this embodiment, the second way is adopted, namely, thepotential enhancing unit 110, the current detecting unit 130, the switchunit 140 and the control unit 120 are integrated in the level shifter400.

The present disclosure further provides a display apparatus, the displayapparatus includes a level shifter 400. The specific structure of thelevel shifter 400 is described with reference to the above embodiments.All the beneficial effects of the technical solutions of the aboveembodiments are achieved because the display apparatus adopts all thetechnical solutions of all the above embodiments, which will not bedescribed in detail herein.

The foregoing description merely portrays some illustrative embodimentsin accordance with the disclosure and therefore is not intended to limitthe patentable scope of the disclosure. Any equivalent structure or flowtransformations that are made taking advantage of the specification andaccompanying drawings of the disclosure and any direct or indirectapplications thereof in other related technical fields shall all fall inthe scope of protection of the disclosure.

What is claimed is:
 1. A gate driver circuit, comprising a potentialenhancing unit, a switch unit, a current detecting unit and a controlunit: the potential enhancing unit, configured to divide a clock signaloutput by a timing sequence controller into two clock signal groupsafter the clock signal being potential enhanced by the potentialenhancing unit, and correspondingly output the two clock signal groupsto two shift register groups on a display panel, to drive the displaypanel to work; the two clock signal groups respectively comprisingsub-clock signals; the switch unit, connected in series between thepotential enhancing unit and the shift registers located at both ends ofthe display panel, and configured to correspondingly switch on or offaccording to a control signal received, to control to output or stopoutputting the clock signal groups; the current detecting unit,connected in series between the potential enhancing unit and the switchunit, or connected in series between the switch unit and the shiftregisters located at both ends of the display panel, configured torespectively detect output current of each sub-clock signal in the twoclock signal groups, and feed back a plurality of current signals to thecontrol unit; and the control unit, configured to receive the pluralityof current signals output by the current detecting unit, and comparecurrent values corresponding to the plurality of current signals with apreset current threshold respectively, in response to a determinationthat the current value of any one of the sub-clock signals in one of theclock signal groups is less than the preset current threshold, output acontrol signal to the switch unit, to control the switch unit to cut offthe output of the clock signal group.
 2. The gate driver circuit ofclaim 1, wherein, a signal input end of the potential enhancing unitconnects to a signal output end of the timing sequence controller, asignal output end of the potential enhancing unit connects to a signalinput end of the current detecting unit, a signal output end of thecurrent detecting unit connects to a signal input end of the switchunit, a first signal output end of the switch unit connects to a signalinput end of the first shift register group of the display panel, asecond signal output end of the switch unit connects to a signal inputend of the second shift register group of the display panel, acontrolled end of the potential enhancing unit, the signal output end ofthe current detecting unit, and a controlled end of the switch unit allconnect to a signal end of the control unit.
 3. The gate driver circuitof claim 1, wherein, the switch unit comprises a first sub-switch unitand a second sub-switch unit, the potential enhancing unit output twoidentical clock signal groups to the shift register at both ends of thedisplay panel, respectively via the first sub-switch unit and the secondsub-switch unit, the controlled end of the first sub-switch unit and thecontrolled end of the second sub-switch unit both connect to a controlend of the control unit.
 4. The gate driver circuit of claim 1, wherein,the switch unit comprises a plurality of sub-switch units, each ofsub-clock signals is output to the shift registers via each of thesub-switch units, and the controlled end of each of the sub-switch unitsrespectively connects to a control end of the control unit.
 5. The gatedriver circuit of claim 4, wherein, the plurality of sub-switch unitsdefined between the current detecting unit and the first shift registerare controlled to be on or off synchronously, and the plurality ofsub-switch units defined between the current detecting unit and thesecond shift register are controlled to be on or off synchronously. 6.The gate driver circuit of claim 4, wherein, each of the sub-switchunits is a metal-oxide semiconductor field effect transistor.
 7. Thegate driver circuit of claim 4, wherein, each of the sub-switch units isa triode.
 8. The gate driver circuit of claim 1, wherein, the currentdetecting unit comprises a plurality of sub-current detecting units,each of the sub-current detecting units respectively detects current ofeach of the sub-clock signals, and respectively feeds back currentsignal to the control unit.
 9. A display apparatus, wherein, the displayapparatus comprises a level shift IC, the level shift IC comprises agate driver circuit as claimed in claim
 1. 10. A level shifter, wherein,the level shifter comprises a gate driver circuit, the gate drivercircuit comprises a potential enhancing unit, a switch unit, a currentdetecting unit and a control unit: the potential enhancing unit,configured to divide a clock signal output by a timing sequencecontroller into two clock signal groups after the clock signal beingpotential enhanced by the potential enhancing unit, and correspondinglyoutput the two clock signal groups to two shift register groups on adisplay panel, to drive the display panel to work; the two clock signalgroups respectively comprising sub-clock signals; the switch unit,connected in series between the potential enhancing unit and the shiftregisters at both ends of the display panel, and configured tocorrespondingly switch on or off according to a control signal received,to control to output or stop outputting the clock signal groups; thecurrent detecting unit, connected in series between the potentialenhancing unit and the switch unit, or in series between the switch unitand the shift registers at both ends of the display panel, configured torespectively detect output current of each sub-clock signal in the twoclock signal groups, and feed back a plurality of current signals to thecontrol unit; and the control unit, configured to receive the pluralityof current signals output by the current detecting unit, and comparecurrent values corresponding to the plurality of current signals with apreset current threshold respectively, in response to a determinationthat the current value of any one of the sub-clock signals in one of theclock signal groups is less than the preset current threshold, output acontrol signal to the switch unit, to control the switch unit to cut offthe output of the clock signal group.
 11. The level shifter of claim 10,wherein, a signal input end of the potential enhancing unit connects toa signal output end of the timing sequence controller, a signal outputend of the potential enhancing unit connects to a signal input end ofthe current detecting unit, a signal output end of the current detectingunit connects to a signal input end of the switch unit, a first signaloutput end of the switch unit connects to a signal input end of thefirst shift register group of the display panel, a second signal outputend of the switch unit connects to a signal input end of the secondshift register group of the display panel, a controlled end of thepotential enhancing unit, the signal output end of the current detectingunit, and a controlled end of the switch unit all connect to a signalend of the control unit.
 12. The level shifter of claim 10, wherein, theswitch unit comprises a first sub-switch unit and a second sub-switchunit, the potential enhancing unit output two identical clock signalgroups to the shift register at both ends of the display panel,respectively via the first sub-switch unit and the second sub-switchunit, the controlled end of the first sub-switch unit and the controlledend of the second sub-switch unit both connect to a control end of thecontrol unit.
 13. The level shifter claim 10, wherein, the switch unitcomprises a plurality of sub-switch units, each of sub-clock signals isoutput to the shift registers via each of the sub-switch units, and thecontrolled end of each of the sub-switch units respectively connects toa control end of the control unit.
 14. The level shifter of claim 13,wherein, the plurality of sub-switch units defined between the currentdetecting unit and the first shift register are controlled to be on oroff synchronously, and the plurality of sub-switch units defined betweenthe current detecting unit and the second shift register are controlledto be on or off synchronously.
 15. The level shifter of claim 13,wherein, each of the sub-switch units is a metal-oxide semiconductorfield effect transistor.
 16. The level shifter of claim 13, wherein,each of the sub-switch units is a triode.
 17. The level shifter of claim10, wherein, the current detecting unit comprises a plurality ofsub-current detecting units, each of the sub-current detecting unitsrespectively detects current of each of the sub-clock signals, andrespectively feeds back current signal to the control unit.
 18. Thelevel shifter of claim 10, wherein, the potential enhancing unit, thecurrent detecting unit, the switch unit, and the control unit areintegrated in the level shifter.